IBM’s NanoStack: A 100‑Story Skyscraper of Tiny Transistors

Thu Jun 25 2026 13:51:10 GMT+0000 (Coordinated Universal Time)

IBM unveils a sub‑1 nm chip design—NanoStack—cramming 100 billion transistors onto a fingernail, delivering 50 % faster performance and 70 % more energy efficiency.

IBM’s latest chip architecture, NanoStack, incorporates three‑dimensional transistor stacking to reach sub‑1‑nanometre scale, potentially fitting 100 billion transistors on a fingernail‑sized chip. The prototype outperforms IBM’s own 2 nm chips by 50 % and cuts energy use by 70 %. Though production could be years away, the design promises a major extension to Moore’s Law, tackling the challenges of heat and leakage as transistor heights shrink.

IBM’s NanoStack: A 100‑Story Skyscraper of Tiny Transistors

IBM has unveiled a new chip architecture that could cram 100 billion transistors onto a fingernail‑sized piece of silicon, promising 50 % performance gain and 70 % energy efficiency improvements over its own 2 nm chips.

The design, called NanoStack, is the first known sub‑1 nm technology and features 3‑D stacking of transistor layers that researchers liken to a 100‑story skyscraper. In a prototype, IBM demonstrated a layered silicon chip that outperformed its 2 nm counterpart by 50 % while drawing 30 % less power.

“With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, IBM Research director.

While the prototype shows promise, IBM cautions that commercial production may take several years. Engineers will need to solve challenges such as heat dissipation—heat rises through the layers—and leakage that can occur if the inter‑layer gaps become too thin.

Moore’s Law, which observes transistor doubling every two years, has started to slow as the density of transistors approaches the limits of two‑nanometre nodes. NanoStack’s vertical, multi‑layer approach offers a way to extend this trend, leveraging 3‑D design to squeeze more transistors into a given silicon area.

IBM’s ambition places it ahead of competitors such as Samsung and Intel, whose 3‑D chips are comparable to 30–50‑story buildings. If NanoStack can be scaled, it would mark a significant milestone in semiconductor miniaturisation, pushing the boundaries of what silicon can do in the digital age.